The Edge Computing Systems (ECS) department focuses on the development of smart detectors within the TID Instrumentation Division (ID). Smart detectors are the evolution of the current [SH1] generation of detectors (i.e. all data is transmitted for offline processing) where real time algorithms are used for data pre-processing[SH2] and data reduction. The ECS team aims to bring the power of smart algorithms and heterogeneous processing units as close as possible to the sensors, creating a rich environment for real-time information extraction.
Examples of future smart detectors are the ePixHR detectors running at 5,000 frames per second (fps). This is the first system that implements a direct path to edge computing systems for image processing inside Field Programmable Gate Arrays (FPGAs).
The ePixHR version with 2 megapixels, depicted below, is another 5,000 fps detector system that enables such processing.
Near future systems will support even higher [SH1] data rates as detectors approach 100 kfps with full frame readout and 1,000 kfps with sparse readout ASICs. The next generation of systems with multi-gigabit transceivers (GTs) require data reduction to cope with the large amount of data produced by the ASICs, which will be greater than what can be streamed out of the detector systems to the users.
SLAC continues to develop libraries of algorithms to implement Machine Learning (ML) in hardware (i.e. FPGA) using high level synthesis methodology. We are also exploring the methodology to expand the target technology to include custom Application Specific Integrated Circuit (ASIC) for ML inference and rule-based algorithms. Our diverse team of engineers, physicists and data analysists work together to create data processing approaches that are scalable and appropriate for edge processing hardware, while providing the data reduction required for modern instrumentation. As the algorithms move from central servers to edge devices, the number of resources available becomes reduced and data visibility limited to partial images. These challenges motivate us to study distributed transformer and TinyML models.
Advancing the edge computing capabilities with novel processing units
In terms of hardware platforms, we are exploring innovative Commercial off-the-shelf (COTS) and, in partnership with the TID-IC department, custom systems with embedded GPU on the same die as the ASIC. These developments have been motivated by the goals to support multiple scientific experiments with real-time data processing, reducing power per operation, maximizing information extraction while minimizing data transfer rate,[SH1] performing low latency and high throughput operation towards streaming and processing of multi-megapixel images in less than 10 us.